C167CS datasheet(34/517 Pages) INFINEON

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C167CS

Derivatives

Architectural Overview

User’s Manual

2-17

V2.0, 2000-07

Capture/Compare (CAPCOM) Units

The two CAPCOM units support generation and control of timing sequences on up to

32 channels with a maximum resolution of 8 CPU clock cycles. The CAPCOM units are

typically used to handle high speed IO tasks such as pulse and waveform generation,

pulse width modulation (PWM), Digital to Analog (D/A) conversion, software timing, or

time recording relative to external events.

Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time

bases for the capture/compare register array.

The input clock for the timers is programmable to several prescaled values of the internal

CPU clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.

This provides a wide range of variation for the timer period and resolution and allows

precise adjustments to the application specific requirements. In addition, external count

inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare

registers relative to external events.

Both of the two capture/compare register arrays contain 16 dual purpose capture/

compare registers, each of which may be individually allocated to either CAPCOM timer

T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.

Each register has one port pin associated with it which serves as an input pin for

triggering the capture function, or as an output pin to indicate the occurrence of a

compare event.

When a capture/compare register has been selected for capture mode, the current

contents of the allocated timer will be latched (captured) into the capture/compare

generated. Either a positive, a negative, or both a positive and a negative external signal

transition at the pin can be selected as the triggering event. The contents of all registers

which have been selected for one of the five compare modes are continuously compared

with the contents of the allocated timers. When a match occurs between the timer value

and the value in a capture/compare register, specific actions will be taken based on the

selected compare mode.

Pulse Width Modulation Unit

The PWM Unit supports the generation of up to four independent high-speed PWM

signals. It allows to generate standard (edge aligned) PWM signals as well as

symmetrical (center aligned) PWM signals. In Burst Mode two channels may be

combined with their output signals ANDed, where one channel gates the output signal

of the other channel. Single Shot Mode allows to generate single output pulses

(retriggerable) under software control. Each PWM channel is controlled by an up/down

counter with associated reload and compare registers. The polarity of the PWM output

signals may be controlled via the respective port output latch (combination via EXOR).

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