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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-31

V2.0, 2000-07

The Multiply/Divide Low Register MDL

This register is a part of the 32-bit multiply/divide register, which is implicitly used by the

CPU, when it performs a multiplication or a division. After a multiplication, this non-bit

addressable register represents the low order 16 bits of the 32-bit result. For long

divisions, the MDL register must be loaded with the low order 16 bits of the 32-bit

dividend before the division is started. After any division, register MDL represents the

16-bit quotient.

Whenever this register is updated via software, the Multiply/Divide Register In Use

(MDRIU) flag in the Multiply/Divide Control register (MDC) is set to ‘1’. The MDRIU flag

is cleared, whenever the MDL register is read via software.

When a multiplication or division is interrupted before its completion and when a new

multiply or divide operation is to be performed within the interrupt service routine,

results.

A detailed description of how to use the MDL register for programming multiply and

divide algorithms can be found in Chapter 22.

MDL

Multiply/Divide Low Reg.

SFR (FE0EH/07H)

Reset Value: 0000H

9876

543210

mdl

rwh

Bit

Function

mdl

Specifies the low order 16 bits of the 32-bit multiply and divide reg. MD.

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