C167CS datasheet(103/517 Pages) INFINEON

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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-20

V2.0, 2000-07

5.5

Interrupt Response Times

The interrupt response time defines the time from an interrupt request flag of an enabled

interrupt source being set until the first instruction (I1) being fetched from the interrupt

vector location. The basic interrupt response time for the C167CS is 3 instruction cycles.

Figure 5-4

Pipeline Diagram for Interrupt Response Time

All instructions in the pipeline including instruction N (during which the interrupt request

flag is set) are completed before entering the service routine. The actual execution time

for these instructions (e.g. waitstates) therefore influences the interrupt response time.

In Figure 5-4 the respective interrupt request flag is set in cycle 1 (fetching of

instruction N). The indicated source wins the prioritization round (during cycle 2). In

cycle 3 a TRAP instruction is injected into the decode stage of the pipeline, replacing

instruction N + 1 and clearing the source’s interrupt request flag to ‘0’. Cycle 4 completes

the injected TRAP instruction (save PSW, IP and CSP, if segmented mode) and fetches

the first instruction (I1) from the respective vector location.

All instructions that entered the pipeline after setting of the interrupt request flag (N + 1,

N + 2) will be executed after returning from the interrupt service routine.

The minimum interrupt response time is 5 states (10 TCL). This requires program

execution from the internal code memory, no external operand read requests and setting

the interrupt request flag during the last state of an instruction cycle. When the interrupt

request flag is set during the first state of an instruction cycle, the minimum interrupt

response time under these conditions is 6 state times (12 TCL).

The interrupt response time is increased by all delays of the instructions in the pipeline

that are executed before entering the service routine (including N).

MCT04332

Pipeline Stage

FETCH

DECODE

EXECUTE

WRITEBACK

Cycle 1

N - 1

N - 2

N - 3

Cycle 2

N + 1

N - 1

N - 2

Cycle 3

N + 2

TRAP (1)

N - 1

Cycle 4

TRAP (2)

TRAP

IR-Flag

Interrupt Response Time

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