C167CS datasheet(107/517 Pages) INFINEON

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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-24

V2.0, 2000-07

• When internal hold conditions between instruction pairs N – 2/N– 1 or N – 1/N occur,

the minimum PEC response time may be extended by 1 state time for each of these

conditions.

• When instruction N reads an operand from the internal code memory, or when N is a

call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum PEC response

time may additionally be extended by 2 state times during internal code memory

program execution.

• In case instruction N reads the PSW and instruction N – 1 has an effect on the

condition flags, the PEC response time may additionally be extended by 2 state times.

The worst case PEC response time during internal code memory program execution

adds to 9 state times (18 TCL).

Any reference to external locations increases the PEC response time due to pipeline

related access priorities. The following conditions have to be considered:

• Instruction fetch from an external location

• Operand read from an external location

• Result write-back to an external location

Depending on where the instructions, source and destination operands are located,

there are a number of combinations. Note, however, that only access conflicts contribute

to the delay.

A few examples illustrate these delays:

• The worst case interrupt response time including external accesses will occur, when

instructions N and N + 1 are executed out of external memory, instructions N – 1 and

N require external operand read accesses and instructions N – 3, N – 2 and N – 1

write back external operands. In this case the PEC response time is the time to

perform 7 word bus accesses.

• When instructions N and N + 1 are executed out of external memory, but all operands

for instructions N – 3 through N – 1 are in internal memory, then the PEC response

time is the time to perform 1 word bus access plus 2 state times.

Once a request for PEC service has been acknowledged by the CPU, the execution of

the next instruction is delayed by 2 state times plus the additional time it might take to

fetch the source operand from internal code memory or external memory and to write the

destination operand over the external bus in an external program environment.

Note: A bus access in this context includes all delays which can occur during an external

bus cycle.

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