C167CS datasheet(106/517 Pages) INFINEON

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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-23

V2.0, 2000-07

5.6

PEC Response Times

The PEC response time defines the time from an interrupt request flag of an enabled

interrupt source being set until the PEC data transfer being started. The basic PEC

response time for the C167CS is 2 instruction cycles.

Figure 5-5

Pipeline Diagram for PEC Response Time

In Figure 5-5 above the respective interrupt request flag is set in cycle 1 (fetching of

instruction N). The indicated source wins the prioritization round (during cycle 2). In

cycle 3 a PEC transfer “instruction” is injected into the decode stage of the pipeline,

suspending instruction N + 1 and clearing the source’s interrupt request flag to ‘0’.

Cycle 4 completes the injected PEC transfer and resumes the execution of instruction

N+ 1.

All instructions that entered the pipeline after setting of the interrupt request flag (N + 1,

N + 2) will be executed after the PEC data transfer.

Note: When instruction N reads any of the PEC control registers PECC7 … PECC0,

while a PEC request wins the current round of prioritization, this round is repeated

and the PEC data transfer is started one cycle later.

The minimum PEC response time is 3 states (6 TCL). This requires program execution

from the internal code memory, no external operand read requests and setting the

interrupt request flag during the last state of an instruction cycle. When the interrupt

request flag is set during the first state of an instruction cycle, the minimum PEC

response time under these conditions is 4 state times (8 TCL).

The PEC response time is increased by all delays of the instructions in the pipeline that

are executed before starting the data transfer (including N).

MCT04333

Pipeline Stage

FETCH

DECODE

EXECUTE

WRITEBACK

Cycle 1

N - 1

N - 2

N - 3

Cycle 2

N + 1

N - 1

N - 2

Cycle 3

N + 2

PEC

N - 1

Cycle 4

N + 2

N + 1

PEC

IR-Flag

PEC Response Time

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