C167CS datasheet(110/517 Pages) INFINEON

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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-27

V2.0, 2000-07

the request flag. In all three cases, the contents of the allocated CAPCOM timer will be

latched into capture register CCx, independent whether the timer is running or not. When

the interrupt enable bit CCxIE is set, a PEC request or an interrupt request for vector

CCxINT will be generated.

Pins T2IN or T4IN can be used as external interrupt input pins when the associated

auxiliary timer T2 or T4 in block GPT1 is configured for capture mode. This mode is

selected by programming the mode control fields T2M or T4M in control registers

T2CON or T4CON to 101B. The active edge of the external input signal is determined by

bit fields T2I or T4I. When these fields are programmed to X01B, interrupt request flags

T2IR or T4IR in registers T2IC or T4IC will be set on a positive external transition at pins

T2IN or T4IN, respectively. When T2I or T4I are programmed to X10B, then a negative

external transition will set the corresponding request flag. When T2I or T4I are

programmed to X11B, both a positive and a negative transition will set the request flag.

In all three cases, the contents of the core timer T3 will be captured into the auxiliary

timer registers T2 or T4 based on the transition at pins T2IN or T4IN. When the interrupt

enable bits T2IE or T4IE are set, a PEC request or an interrupt request for vector T2INT

or T4INT will be generated.

Pin CAPIN differs slightly from the timer input pins as it can be used as external interrupt

input pin without affecting peripheral functions. When the capture mode enable bit T5SC

in register T5CON is cleared to ‘0’, signal transitions on pin CAPIN will only set the

interrupt request flag CRIR in register CRIC, and the capture function of register

CAPREL is not activated.

So register CAPREL can still be used as reload register for GPT2 timer T5, while pin

CAPIN serves as external interrupt input. Bit field CI in register T5CON selects the

effective transition of the external interrupt input signal. When CI is programmed to 01B,

a positive external transition will set the interrupt request flag. CI = 10B selects a negative

transition to set the interrupt request flag, and with CI = 11B, both a positive and a

negative transition will set the request flag. When the interrupt enable bit CRIE is set, an

interrupt request for vector CRINT or a PEC request will be generated.

Note: The non-maskable interrupt input pin NMI (sample rate 2 TCL) and the reset input

RSTIN provide another possibility for the CPU to react on an external input signal.

NMI and RSTIN are dedicated input pins, which cause hardware traps.

C167CS Datasheet(PDF) 110 Page - Infineon Technologies AG