C167CS datasheet(114/517 Pages) INFINEON

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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-31

V2.0, 2000-07

5.9

Trap Functions

Traps interrupt the current execution similar to standard interrupts. However, trap

functions offer the possibility to bypass the interrupt system’s prioritization process in

cases where immediate system reaction is required. Trap functions are not maskable

and always have priority over interrupt requests on any priority level.

The C167CS provides two different kinds of trapping mechanisms. Hardware traps are

triggered by events that occur during program execution (e.g. illegal access or undefined

opcode), software traps are initiated via an instruction within the current execution flow.

Software Traps

The TRAP instruction is used to cause a software call to an interrupt service routine. The

trap number that is specified in the operand field of the trap instruction determines which

vector location in the address range from 00’0000H through 00’01FCH will be branched to.

Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector

had occurred. PSW, CSP (in segmentation mode), and IP are pushed on the internal

system stack and a jump is taken to the specified vector location. When segmentation is

enabled and a trap is executed, the CSP for the trap service routine is set to code

segment 0. No Interrupt Request flags are affected by the TRAP instruction. The

interrupt service routine called by a TRAP instruction must be terminated with a RETI

(return from interrupt) instruction to ensure correct operation.

Note: The CPU level in register PSW is not modified by the TRAP instruction, so the

service routine is executed on the same priority level from which it was invoked.

Therefore, the service routine entered by the TRAP instruction can be interrupted

by other traps or higher priority interrupts, other than when triggered by a

hardware trap.

Hardware Traps

Hardware traps are issued by faults or specific system states that occur during runtime

of a program (not identified at assembly time). A hardware trap may also be triggered

intentionally, e.g. to emulate additional instructions by generating an Illegal Opcode trap.

The C167CS distinguishes eight different hardware trap functions. When a hardware

trap condition has been detected, the CPU branches to the trap vector location for the

respective trap condition. Depending on the trap condition, the instruction which caused

the trap is either completed or cancelled (i.e. it has no effect on the system state) before

the trap handling routine is entered.

Hardware traps are non-maskable and always have priority over every other CPU activity.

If several hardware trap conditions are detected within the same instruction cycle, the

highest priority trap is serviced (see Table 5-2).

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