C167CS datasheet(115/517 Pages) INFINEON

115 / 517 page

C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-32

V2.0, 2000-07

PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and

the CPU level in register PSW is set to the highest possible priority level (i.e. level 15),

disabling all interrupts. The CSP is set to code segment zero, if segmentation is enabled.

A trap service routine must be terminated with the RETI instruction.

The eight hardware trap functions of the C167CS are divided into two classes:

Class A traps are

• external Non-Maskable Interrupt (NMI)

• Stack Overflow

• Stack Underflow Trap

These traps share the same trap priority, but have an individual vector address.

Class B traps are

• Undefined Opcode

• Protection Fault

• Illegal Word Operand Access

• Illegal Instruction Access

• Illegal External Bus Access Trap

These traps share the same trap priority, and the same vector address.

The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the

kind of trap which caused the exception. Each trap function is indicated by a separate

request flag. When a hardware trap occurs, the corresponding request flag in register

TFR is set to ‘1’.

The reset functions (hardware, software, watchdog) may be regarded as a type of trap.

Reset functions have the highest system priority (trap priority III).

Class A traps have the second highest priority (trap priority II), on the 3rd rank are class

B traps, so a class A trap can interrupt a class B trap. If more than one class A trap occur

at a time, they are prioritized internally, with the NMI trap on the highest and the stack

underflow trap on the lowest priority.

All class B traps have the same trap priority (trap priority I). When several class B traps

get active at a time, the corresponding flags in the TFR register are set and the trap

service routine is entered. Since all class B traps have the same vector, the priority of

service of simultaneously occurring class B traps is determined by software in the trap

service routine.

A class A trap occurring during the execution of a class B trap service routine will be

serviced immediately. During the execution of a class A trap service routine, however,

any class B trap occurring will not be serviced until the class A trap service routine is

exited with a RETI instruction. In this case, the occurrence of the class B trap condition

is stored in the TFR register, but the IP value of the instruction which caused this trap is

lost.

C167CS Datasheet(PDF) 115 Page - Infineon Technologies AG

C167CS Datasheet(HTML) 115 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL