6V7 datasheet(175/298 Pages) RENESAS

175 / 298 page

Rev.1.00

May 18, 2004

page 175 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

2.14.13 ID1 data slice

When data slice ID1, ID1 control register of Fig 2.14.20 needs to be set.

Figure 2.14.20 ID1 control register

Figure 2.14.21 ID1 reserved register

b7 b6 b5 b4 b3 b2 b1 b0

ID1 control register

Symbol

IDC0

IDC1

Address

026B16

030B16

When reset

0016

Bit name

Function

R W

Bit symbol

IDC00/IDC10

ID1 slice control bit

ID1 limitation slice select bit

Internal absolute standard

voltage setting bit

b4 b3 b2

0: ID1 slice unused

1: ID1 slice operate

* Must always be set to "0" at ID1 slice unused.

When set to "1", be sure to set bits 4 to 0 = 10000b of

addresses 026616/030616.

0: Set this bit when slice simultaneously with CC21.

1: Set this bit when slice only ID1.

IDC01/IDC11

IDC02/IDC12

IDC03/IDC13

IDC04/IDC14

0 100

Must always be set to "0."

Reserved bit

IDC0b/IDC1b

525i/p Selection bit

Must always be set to "0."

Reserved bit

525p:When ID1 data slice,

Set up bit 4-0 = 00001b at addresses 026616/030616.

Set bit 6 and 5 = 01b of addresses 026A16/030A16.

0:525i set up at CC21, CCX, and ID1 slice

0:525p set up at ID1 slice

Figure 2.14.22 ID1 signal in vertial blanking interval

b7 b6 b5 b4 b3 b2 b1 b0

ID1 reserved register

Symbol

IRSV0

IRSV1

031C16

When reset

Address

031D16

0016

Bit name

Function

R W

Bit symbol

Sync slice setting bit

IRSV06/IRSV16

IRSV07/IRSV17

Must always be set to "1."

–

The contents are unfixed when it reads.

The register only for read-out

Composite

video signal

ID1 reference

detection timing signal

Hsep

ID1 reference bit

* ID1 to ID20 shows ID1 data

Line 20 at 525i

Line 40 at 525p

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