6V7 datasheet(174/298 Pages) RENESAS

174 / 298 page

Rev.1.00

May 18, 2004

page 174 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

2.14.12 Interrupt Request Generating Circuit

The interrupt requests as shown in Table 2.14.2 are generated by combination of the following bits; bits 6

and 7 of the caption position register (addresses 026616/030616). Read out the contents of caption data

registers 1 and 2, CRCC data register, clock run-in detect register and standard clock detect register after

the occurrence of a data slicer interrupt request.

CPS

Occurrence Sources of Interrupt Request at End of Data Slice Line

After slicing line 21

After a line specified by bits 4 to 0 of CPS (Note)

After slicing line 21

Table 2.14.2 Occurrence sources of Interrupt request

CPS: Caption position register

Figure 2.14.19 Data slicer reserved register i (i = 1, 2)

Data slicer reserved register 1

Symbol

Address

When reset

DR01

026816

0016

DR11

030816

0016

Reserved bits

Bit symbol

Bit name

Description

Must always be set to “0”

Figure 2.14.18 CRCC data register

b7 b6 b5 b4 b3 b2 b1 b0

CRCC data register

Symbol

CRC0

CRC1

Address

026D16

030D16

When reset

00?????? 2

Bit name

Function

R W

Bit symbol

CRC00/CRC10 CRCC data register

Data 20-15 of ID1 is stored in bit 5-0.

It is effective, only when "1" is set as the bit 0 of addresses

026B16 and 030B16, and ID1 slice function is operating.

CRC01/CRC11

CRC02/CRC12

CRC03/CRC13

CRC04/CRC14

CRC05/CRC15

Nothing is assigned.

If an attempt to write to these bits, write “0.” The read turns out to be “0.”

Note: It becomes the one-line back specified in 525p caption position register bits 4 to 0 and the data clock

position register bits 6 and 5.

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