6V7 datasheet(170/298 Pages) RENESAS

170 / 298 page

Rev.1.00

May 18, 2004

page 170 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

2.14.7 Reference Voltage Generating Circuit and Comparator

The composite video signal clamped by the clamping circuit is input to the reference voltage generating

circuit and the comparator 1 and 2.

(1) Reference voltage generating circuit

This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in

pulse in line specified by the data slice line specification circuit. Connect a capacitor between the

VHOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage

current may not be generated.

Note: It takes a few tens of lines to generate slice voltage until the slice voltage becomes stable after

the data slicer is started. In this period, the slice data becomes unstable. For this reason, take

stabilization time into consideration when programming.

(2) Comparator 1

The comparator 1 compares the voltage of the composite video signal with the voltage (reference

voltage) generated in the reference voltage generating circuit, and converts the composite video sig-

nal into a digital value.

(3) Comparator 2

The comparator 2 compares the absolute standard voltage generated inside from the voltage and

power supply voltage of a composite video signal, and converts the composite video signal into a

digital value.

2.14.8 CC Start Bit • ID1 Reference Detecting Circuit

This circuit detects a CC start bit • ID1 reference bit at line decided in the data slice line specification

circuit.

In the case of CC start bit

1) Detect a clock run impulse at counting the input pulse of a data slice line.

2) When a clock run impulse is detected, the sampling clock outputted from a timing generating circuit

detects a start bit pattern, and judge CC start bit.

In the case of ID1 reference bit

1) Detect ID1 reference bit all over the window generated after fixed time from Hsep in a timing signal

generating circuit.

2.14.9 Clock Run-in Determination Circuit

Clock run in judging

By counting the number of pulses all over the specific window of a data slice line, it judges that it is clock

run in. When it judges with having no clock run in, the completion flag of a caption data latch is not set to

1. Moreover, the number of standard clocks counted in clock run impulse 1 cycle is stored in the bits 7-3

of a clock run in detection register (addresses 026916/030916).

ID1 reference bit judging

The number of standard clocks counted during fixed of ID1 reference bit is stored in the bits 5-0 of a

standard clock detection register (addresses 026C16/the 030C16). Read these bits after generating of

data slicer interruption ("(12) interruption demand generating circuit").

Clock run-in detection register is shown in Fig. 2.14.11, standard clock detection register is shown in Fig.

2.14.12.

6V7 Datasheet(PDF) 170 Page - Renesas Technology Corp

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