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6V7 Datasheet(PDF) 167 Page - Renesas Technology Corp |
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6V7 Datasheet(HTML) 167 Page - Renesas Technology Corp |
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167 / 298 page  Rev.1.00 May 18, 2004 page 167 of 296 M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP 2.14.5 Timing Signal Generating Circuit This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal syn- chronous signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer control register 1 (address 026016/030016) to “1.” The reference clock is the HSYNC signal can be used as a count source instead of the composite sync signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 026016/030016). For the pins HLF, connect a resistor and a capacitor as shown in Figure 2.14.1 Make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be generated. Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. In this period, various timing signals, Hsep signals and Vsep signals become unstable. For this reason, take stabilization time into consideration when programming. |
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