6V7 datasheet(166/298 Pages) RENESAS

166 / 298 page

Rev.1.00

May 18, 2004

page 166 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

2.14.2 Clamping Circuit and Low-pass Filter

The clamp circuit clamps the sync. tip part of the composite video signal input from the CVIN pin. The low-

pass filter attenuates the noise of clamped composite video signal. The CVIN pin to which composite video

signal is input requires a capacitor (0.1

µF) coupling outside. Pull down the CVIN pin with a resistor of

hundreds of kiloohms to 1 M

Ω. In addition, we recommend to install externally a simple low-pass filter

using a resistor and a capacitor at the CVIN pin (refer to Figure 2.14.1 and notes).

2.14.3 Sync Slice Circuit

This circuit takes out a composite sync signal from the output signal of the low-pass filter.

Set bit 6 and 7 to 11b of ID1 reserved register (addresses 037C16 and 031D16) show in Fig 2.14.21.

2.14.4 Synchronous Signal Separation Circuit

This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the compos-

ite sync signal taken out in the sync slice circuit.

(1) Horizontal synchronous signal (Hsep)

A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync

signal.

(2) Vertical synchronous signal (Vsep)

As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit

4 of the data slicer control register 2 (address 026116/030116).

•Method 1 The “L” level width of the composite sync signal is measured. If this width exceeds a

certain time, a Vsep signal is generated in synchronization with the rising of the timing

signal immediately after this “L” level.

•Method 2 The “L” level width of the composite sync signal is measured. If this width exceeds a

certain time, it is detected whether a falling of the composite sync signal exits or not in the

“L” level period of the timing signal immediately after this “L” level. If a falling exists, a Vsep

signal is generated in synchronization with the rising of the timing signal (refer to Figure

2.14.6).

Figure 2.14.6 shows a Vsep generating timing. The timing signal shown in the figure is generated from the

reference clock which the timing generating circuit outputs.

Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the

composite sync signal. As shown in Figure 2.14.7, when the A level matches the B level, this bit is “0.” In

the case of a mismatch, the bit is “1.”

Figure 2.14.6 Vsep generating timing (method 2)

Composite sync

“L” level width is measured

“L” level period of a timing signal

Timing

signal

A Vsep signal is generated at a rising of the timing signal

immediately after the “L” level width of the composite

sync signal exceeds a certain time.

Vsep signal

Figure 2.14.7 Determination of v-pulse waveform

Composite

sync signal

Bit 5 of

DSC02/DSC12

6V7 Datasheet(PDF) 166 Page - Renesas Technology Corp

6V7 Datasheet(HTML) 166 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL