6V7 datasheet(165/298 Pages) RENESAS

165 / 298 page

Rev.1.00

May 18, 2004

page 165 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

Figures 2.14.4 and 2.14.5 the data slicer control registers.

Figure 2.14.4 Data slicer control register 1

Figure 2.14.5 Data slicer control register 2

b7 b6 b5 b4 b3 b2 b1 b0

Data slicer control register 1

Reserved bits

00 0

Definition of fields 1 (F1) and 2 (F2)

Hsep

Vsep

F1:

Hsep

Vsep

F2:

R W

Bit name

Must always be set to “0”

Symbol

Address

When reset

DSC01

DSC11

026016

030016

0016

Bit symbol

DSC010/

DSC110

DSC011/

DSC111

DSC012/

DSC112

Reference clock source

selection bit

Data slicer and timing signal

generating circuit control bit

0: F2

1: F1

Selection bit of data slice reference

voltage generating field

0: Stopped (Set at slicer unused)

1: Operating (Set at slicer used)

0: Video signal (Set “0”, normally)

1: HSYNC signal

At two lines: CC21, and CCX or ID1 are sliced

(notes 1 and 2)

1: Select F1, normally

At only ID1 is sliced

0/1: Select either (note 3)

Notes 1. Selected by addresses 026616, 026B16, 030616 and 030B16 register setting.

2. When ID1 slice is set, addresses 026B16 and 030B16 are need to be set.

3. It is required to superimpose F1 and F2 on the same data.

4. CC21: line 21data of CC format.

CCX: the line data which can be selected by addresses 026616 and 030616 of CC format.

ID1: ID1 format data.

525p:When ID1 data slice

X:This bit setting is invalid.

Function

b7 b6 b5 b4 b3 b2 b1 b0

Data slicer control register 2

Caption data latch

completion flag 1

Reserved bit

Read-only

Test bit

0: F2

1: F1

Field determination flag

0: Method (1)

1: Method (2)

Vertical synchronous signal

(Vsep) generating method

selection bit

0: Match

1: Mismatch

V-pulse shape

determination flag

Bit name

Definition of fields 1 (F1) and 2 (F2)

Hsep

Vsep

F1:

Hsep

Vsep

F2:

Bit symbol

DSC020/

DSC120

DSC023/

DSC123

DSC024/

DSC124

DSC025/

DSC125

Symbol

Address

When reset

DSC02

DSC12

026116

?0?0??0?2

030116

?0?0??0?2

Must always be set to “0”

Reserved bit

Must always be set to “0”

Read-only

Test bit

When two lines of CC21 and CCX are sliced,

0: Incompletion of CC21 caption data latch, or no clock run-in.

1: Completion of CC21 caption data latch, and clock run-in.

When only CCX is sliced,

0: Incompletion of CCX caption data latch, or no clock run-in.

1: Completion of CCX caption data latch, and clock run-in.

When only ID1 is sliced,

0: Incompletion of ID1 caption data latch.

1: Completion of ID1 caption data latch.

note: A flag is reset by 0 in falling of vertical synchronized signal.

(*)This flag is invalid at 026B16 and 030B16 at the time of 525p selection.

Function

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