6V7 datasheet(169/298 Pages) RENESAS

169 / 298 page

Rev.1.00

May 18, 2004

page 169 of 296

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP

Figure 2.14.9 Caption position register

Field and Line to Generate Slice Voltage

• Field specified by bit 1 of DSC01/DSC11

• Line 21 (total 1 line)

• Field specified by bit 1 of DSC01/DSC11

• A line specified by bits 4 to 0 of CPS0/CPS1

(total 1 line) (See note 3)

• Field specified by bit 1 of DSC01/DSC11

• Line 21 (total 1 line)

• Field specified by bit 1 of DSC01/DSC11

• Line 21 and a line specified by bits 4 to 0 of CPS0/

CPS1 (total 2 lines) (See note 2)

Field and Line to Be Sliced Data

• Both fields of F1 and F2

• Line 21 and a line specified by bits 4 to 0 of CPS0/

CPS1 (total 2 lines) (See note 2)

• Both fields of F1 and F2

• A line specified by bits 4 to 0 of CPS0/CPS1

(total 1 line) (See note 3)

• Both fields of F1 and F2

• Line 21 (total 1 line)

• Both fields of F1 and F2

• Line 21 and a line specified by bits 4 to 0 of CPS0/

CPS1 (total 2 lines) (See note 2)

CPS0/CPS1

Notes 1: DSC01/DSC11 is data slicer control register 1.

CPS0/CPS1 is caption position register.

2: Set the value of “0016” – “1016” to bits 4 to 0 of CPS0/CPS1.

3: Set the value of “0016” – “1F16” to bits 4 to 0 of CPS0/CPS1.

Table 2.14.1 Specification of data slice line

b7 b6 b5 b4 b3 b2 b1 b0

Caption position register

Caption position bits

Bit symbol

CPS00/CPS10

CPS01/CPS11

CPS02/CPS12

CPS03/CPS13

CPS04/CPS14

CPS05/CPS15

CPS06/CPS16

CPS07/CPS17

Symbol

Address

When reset

CPS0

CPS1

026616

00?000002

030616

00?000002

Refer to table 2.14.1 at slice CC21 or CCX.

Set bits 6 and 7 = 00b or 01b when ID1 slice.

Slice line mode

specification bits

(in 1 field)

Caption data latch

completion flag 2

Set caption position (CCX or ID1).

For CCX, refer to Table 2.14.1.

For ID1 slice, set bits 0 to 4 = 10000b (select 20)

When two lines of CC21 and CCX are sliced,

0: Incompletion of CCX caption data latch, or no clock run-in.

1: Completion of CCX caption data latch, and clock run-in.

When two lines of CC21 and ID1 are sliced,

0: Incompletion of ID1 caption data latch.

1: Completion of ID1 caption data latch.

This bit is invalid when slice only any one line of CC21,

CCX and ID1.

note: A flag is reset by 0 in rising of vertical synchronized signal.

525p:When ID1 data slice, set bit 7 and 6 = 01b.

Function

Bit name

525p:When ID1 data slice,

set up bit 4-0 = 00001b (line 41 selection).

(*) addresses 026A16 and 030A16

bit 6 and 5 = 01b need to be set up.

b7 b6 b5 b4 b3 b2 b1 b0

Slice standard voltage selection register

Slice standard voltage

selection bit

Reserved bits

Symbol

SBV0

SBV1

Address

26716

30716

When reset

0016

Bit name

Function

R W

Bit symbol

SVB00/SVB10

SVB01/SVB11

Must be set to “0.”

b1, b0

Standard voltage selection by standard voltage

generating circuit.

Internal absolute standard voltage selection.

CC21 is the voltage by the standard voltage generating

circuit. CCX or ID1 is internal absolute standard voltage

selection.

Do not set

000

Figure 2.14.10 Slice standard voltage selection register

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