M37274EFSP datasheet(36/148 Pages) RENESAS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37274EFSP

PRELIMINARY

Notice:

This

is not

a final

specification.

Some

paramentic

limits

are

subject

to change.

MITSUBISHI MICROCOMPUTERS

VREF

256

✕ (n – 0.5)

1 to 255

Note: VREF indicates the voltage of internal VCC.

Fig. 29. Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion

(6) Conversion Method

1Set bit 7 of the interrupt input polarity register (address 021216) to

“1” to generate an interrupt request at completion of A-D conver-

sion.

2Set the A-D conversion • INT3 interrupt request bit to “0” (even

when A-D conversion is started, the A-D conversion • INT3 inter-

rupt reguest bit is not set to “0” automatically).

3When using A-D conversion interrupt, enable interrupts by setting

A-D conversion • INT3 interrupt request bit to “1” and setting the

interrupt disable flag to “0.”

4Set the VCC connection selection bit to “1” to connect VCC to the

resistor ladder.

5Select analog input pins by the analog input selection bit of the A-

D control register.

6Set the A-D conversion completion bit to “0.” This write operation

starts the A-D conversion. Do not read the A-D conversion regis-

ter during the A-D conversion.

7Verify the completion of the conversion by the state (“1”) of the

A-D conversion completion bit, the state (“1”) of A-D conversion •

INT3 interrupt reguest bit, or the occurrence of an A-D conversion

interrupt.

8Read the A-D conversion register to obtain the conversion results.

Note : When the ladder resistor is disconnect from VCC, set the VCC

connection selection bit to “0” between steps

7and 8.

(7) Internal Operation

When the A-D conversion starts, the following operations are auto-

matically performed.

1The A-D conversion register is set to “0016.”

2The most significant bit of the A-D conversion register becomes

“1, ” and the comparison voltage “Vref” is input to the comparator.

At this point, Vref is compared with the analog input voltage “VIN .”

3Bit 7 is determined by the comparison results as follows.

When Vref < VIN : bit 7 holds “1”

When Vref > VIN : bit 7 becomes “0”

With the above operations, the analog value is converted into a digi-

tal value. The A-D conversion terminates in a maximum of 50 ma-

chine cycles (12.5 µs at f(XIN) = 8 MHz) after it starts, and the con-

version result is stored in the A-D conversion register.

An A-D conversion interrupt request occurs at the same time as A-D

conversion completion, the A-D conversion • INT3 interrupt request

bit becomes “1.” The A-D conversion completion bit also becomes

“1.”

Table 3. Expression for Vref and VREF

A-D conversion register contents “n”

(decimal notation)

Vref (V)

12 3 45 6 7 8

1 00 0 0 0 0 0

10 0

0 0 0

10 0 0 0 0

12 3 4 5 6 7

VREF

512

–

VREF

512

–

±±

VREF

512

–

00 0 0 0

0 0 0

Contents of A-D conversion register

Reference voltage (Vref)

[V]

A-D conversion start

1st comparison start

3rd comparison start

8th comparison start

2nd comparison start

Digital value corresponding to

analog input voltage.

A-D conversion completion

(8th comparison completion)

VREF

512

–

VREF

256

.......

: Value determined by mth (m = 1 to 8) result

.....

M37274EFSP Datasheet(PDF) 36 Page - Renesas Technology Corp

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