M37274EFSP datasheet(60/148 Pages) RENESAS

60 / 148 page

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37274EFSP

PRELIMINARY

Notice:

This

is not

a final

specification.

Some

paramentic

limits

are

subject

to change.

s Bit 6: Communication Mode Specification Bit (transfer direction

specification bit: TRX)

This bit decides the direction of transfer for data communication. When

this bit is “0,” the reception mode is selected and the data of a trans-

mitting device is received. When the bit is “1,” the transmission mode

is selected and address data and control data are output into the

SDA in synchronization with the clock generated on the SCL.

When the ALS bit of the I2C control register (address 00F916) is “0”

in the slave reception mode is selected, the TRX bit is set to “1”

(transmit) if the least significant bit (R/W bit) of the address data trans-

mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is

“0,” the TRX bit is cleared to “0” (receive).

The TRX bit is cleared to “0” in one of the following conditions.

• When arbitration lost is detected.

• When a STOP condition is detected.

• When occurence of a START condition is disabled by the START

condition duplication prevention function (Note).

• With MST = “0” and when a START condition is detected.

• With MST = “0” and when ACK non-return is detected.

• At reset

s Bit 7: Communication Mode Specification Bit (master/slave speci-

fication bit: MST)

This bit is used for master/slave specification for data communica-

tion. When this bit is “0,” the slave is specified, so that a START

condition and a STOP condition generated by the master are re-

ceived, and data communication is performed in synchronization with

the clock generated by the master. When this bit is “1,” the master is

specified and a START condition and a STOP condition are gener-

ated, and also the clocks required for data communication are gen-

erated on the SCL.

The MST bit is cleared to “0” in one of the following conditions.

•Immediately after completion of 1-byte data transmission when ar-

bitration lost is detected

•When a STOP condition is detected.

•When occurence of a START condition is disabled by the START

condition duplication preventing function (Note).

•At reset

Note: The START condition duplication prevention function disables

the START condition generation, reset of bit counter reset,

and SCL output, when the following condition is satisfied:

• a START condition is set by another master device.

Fig. 56. I2C Status Register

b7 b6 b5 b4 b3 b2 b1 b0

I2C status register (S1) [Address 00F816]

I2C Status Register

6, 7

b7 b6

0 : Slave recieve mode

1 : Slave transmit mode

0 : Master recieve mode

1 : Master transmit mode

Name

Functions

After reset RW

Communication mode

specification bits

(TRX, MST)

0 : Bus free

1 : Bus busy

Bus busy flag (BB)

0 : Interrupt request issued

1 : No interrupt request issued

I2C-BUS interface interrupt

request bit (PIN)

0 : Not detected

1 : Detected

Arbitration lost detecting flag

(AL) (See note)

0 : Address mismatch

1 : Address match

Slave address comparison

flag (AAS) (See note)

0 : No general call detected

1 : General call detected

General call detecting flag

(AD0) (See note)

0 : Last bit = “0 ”

1 : Last bit = “1 ”

Last receive bit (LRB)

(See note)

Note : These bits and flags can be read out, but cannnot be written.

Indeterminate R—

R—

M37274EFSP Datasheet(PDF) 60 Page - Renesas Technology Corp

M37274EFSP Datasheet(HTML) 60 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL