M37274EFSP datasheet(72/148 Pages) RENESAS

72 / 148 page

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37274EFSP

PRELIMINARY

Notice:

This

is not

a final

specification.

Some

paramentic

limits

are

subject

to change.

MITSUBISHI MICROCOMPUTERS

Fig. 70. Vertical Position Register 1

The vertical position for each block can be set in 1024 steps (where

each step is 1TH (TH: HSYNC cycle)) as values “0016” to “FF16” in

vertical position register 1i (i = 1 to 12) (addresses 022016 to 022B16)

and values “0016” to “0316” in vertical position register 2i (i = 1 to 12)

(addresses 023016 to 023B16). The structure of the vertical position

registers is shown in Figure 70 and 71.

Fig. 71. Vertical Position Register 2

b7 b6 b5 b4 b3 b2 b1 b0

Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 022016 to 022F16]

Name

Functions

After reset

R W

Vertical Position Register 1i

Control bits of vertical

display start positions

(VP1i0 to VP1i7)

(See note 1)

Vertical display start positions

(low-order 8 bits)

TH !

(setting value of low-order 2 bits of VP2i ! 162

+ setting value of low-order 4 bits of VP1i ! 161

+ setting value of low-order 4 bits of VP1i ! 160)

Indeterminate RW

Notes 1: Set values except “00 16” “0116” to VP1i when VP2i is “00 16.”

2: TH is cycle of HSYNC.

b7 b6 b5 b4 b3 b2 b1 b0

Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 023016 to 023F16]

Name

Functions

After reset

R W

Vertical Position Register 2i

0, 1 Control bits of vertical

display start positions

(VP1i0, VP1i1)

(See note 1)

Vertical display start positions

(high-order 2 bits)

TH !

(setting value of low-order 2 bits of VP2i ! 162

+ setting value of low-order 4 bits of VP1i ! 161

+ setting value of low-order 4 bits of VP1i ! 160)

Indeterminate RW

Nothing is assigned. These bits are write disable bits.

When these bits are read out, the values are indeterminate.

Indeterminate R—

Notes 1: Set values except “00 16” “0116” to VP1i when VP2i is “00 16.”

2: TH is cycle of HSYNC.

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