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M37274EFSP Datasheet(PDF) 75 Page - Renesas Technology Corp |
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M37274EFSP Datasheet(HTML) 75 Page - Renesas Technology Corp |
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75 / 148 page ![]() 74 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER M37274EFSP PRELIMINARY Notice: This is not a final specification. Some paramentic limits are subject to change. MITSUBISHI MICROCOMPUTERS (3) Dot Size The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size con- trol circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1, main clock) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1TC. The dot size of the layer 1 is specified by bits 6 to 3 of the block control register. The dot size of the layer 2 is specified by the following bits : bits 3 and 4 of the block control register, bit 6 of the clock source control register. Refer to Figure 65 (the structure of the block control regis- ter), refer to Figure 76 (the structure of the clock source control reg- ister). The block diagram of dot size control circuit is shown in Figure 75. Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode. 2 : The pre-divide ratio of the OSD mode block on the layer 2 must be same as that of the CC mode block on the layer 1 by bit 6 of the clock source control register. 3 : In the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal mode. Refer to “(13) Scan Mode” about the scan mode. Fig. 74. Block Diagram of Dot Size Control Circuit Fig. 75. Definition of Dot Sizes In normal scan mode HSYNC Main clock Synchronous Cycle ! 2 circuit Cycle ! 3 Pre-divide circuit Clock cycle = 1TC Horizontal dot size control circuit Vertical dot size control circuit OSD control circuit Data slicer clock (Note) OSC1 Note: To use data slicer clock, set bit 0 of data slicer control register to “0.” 1 dot Scanning line of F1(F2) Scanning line of F2(F1) 1/2H 1H 2H 3H 3TC 2TC 1TC 1TC |
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