M37274EFSP datasheet(11/148 Pages) RENESAS

11 / 148 page

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER

and ON-SCREEN DISPLAY CONTROLLER

M37274EFSP

PRELIMINARY

Notice:

This

is not

a final

specification.

Some

paramentic

limits

are

subject

to change.

MITSUBISHI MICROCOMPUTERS

FUNCTIONAL DESCRIPTION

Central Processing Unit (CPU)

The M37274EFSP uses the standard 740 Family instruction set. Refer

to the table of 740 Family addressing modes and machine instruc-

tions or the SERIES 740 <Software> User’s Manual for details on

the instruction set.

Machine-resident 740 Family instructions are as follows:

The FST, SLW instruction cannot be used.

The MUL, DIV, WIT and STP instructions can be used.

CPU Mode Register

The CPU mode register contains the stack page selection bit and

internal system clock selection bit. The CPU mode register is allo-

cated at address 00FB16.

Fig. 3. CPU Mode Register

b7 b6 b5 b4 b3 b2 b1 b0

After reset RW

CPU Mode Register

0, 1

3, 4

Name

Functions

Processor mode bits

(CM0, CM1)

0 0: Single-chip mode

0 1:

1 0:

Not available

1 1:

Fix these bits to “1.”

Stack page selection

bit (CM2) (See note)

b1 b0

0: 0 page

1: 1 page

Main Clock (X IN–XOUT)

stop bit

(CM6)

CPU mode register (CPUM) (CM) [Address FB16]

XCOUT drivability

selection bit (CM5)

0: LOW drive

1: HIGH drive

0: Oscillating

1: Stopped

Internal system clock

selection bit

(CM7)

0: XIN–XOUT selected

(high-speed mode)

1: XCIN–XCOUT selected

(high-speed mode)

Note: This bit is set to “1” after the reset release.

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