Electronic Components Datasheet Search
  English  ▼

X  

M37274EFSP Datasheet(PDF) 41 Page - Renesas Technology Corp

Part # M37274EFSP
Description  SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PDF  148 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M37274EFSP Datasheet(HTML) 41 Page - Renesas Technology Corp

Back Button M37274EFSP Datasheet HTML 37Page - Renesas Technology Corp M37274EFSP Datasheet HTML 38Page - Renesas Technology Corp M37274EFSP Datasheet HTML 39Page - Renesas Technology Corp M37274EFSP Datasheet HTML 40Page - Renesas Technology Corp M37274EFSP Datasheet HTML 41Page - Renesas Technology Corp M37274EFSP Datasheet HTML 42Page - Renesas Technology Corp M37274EFSP Datasheet HTML 43Page - Renesas Technology Corp M37274EFSP Datasheet HTML 44Page - Renesas Technology Corp M37274EFSP Datasheet HTML 45Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 41 / 148 page
background image
40
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274EFSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
Fig. 35. Sync Slice Register
(1) Clamping Circuit and Low-pass Filter
This filter attenuates the noise of the composite video signal input
from the CVIN pin. The CVIN pin to which composite video signal is
input requires a capacitor (0.1
µF) coupling outside. Pull down the
CVIN pin with a resistor of hundreds of kiloohms to 1 M . In addition,
we recommend to install externally a simple low-pass filter using a
resistor and a capacitor at the CVIN pin (refer to Figure 25).
(2) Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter. Figure 25 shows the structure of the sync slice
register.
b7 b6 b5 b4 b3 b2 b1 b0
Sync slice register (SSL) [Address 00E3 16]
Sync Slice Register
7
0R W
0R W
Vertical synchronous
signal (Vsep) generating
method selection bit
(SSL7)
0, 2
Fix these bits to “1.”
B
After reset
Functions
Name
RW
0: Method 1
1: Method 2
0001
01
0R W
1,
3 to 6
Fix these bits to “0.”
0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com