HD64F36034 datasheet(330/592 Pages) RENESAS

330 / 592 page

Section 15 Controller Area Network for Tiny (TinyCAN)

Rev. 4.00 Mar. 15, 2006 Page 298 of 556

REJ09B0026-0400

• Message control (MCn0, MCn4 to MCn7 [n = 0 to 3])

• Local acceptance filter mask (LAFMHn1, LAFMHn0, LAFMLn1, and LAFMLn0 [n = 0 to 3])

• Message data (MDn0 to MDn7 [n = 0 to 3])

15.3.1

Test Control Register (TCR)

TCR controls the CDLC test mode.

TCR must be configured in the initial state or in halt mode. For details, see section 15.7, Test

Mode Settings.

Bit

Bit Name

Initial

Value

R/W

Description

TSTMD

R/W

Test Mode

Enables or disables the test mode.

0: TinyCAN in normal mode

1: TinyCAN in test mode

WREC

R/W

CAN Error Counters Write Enable

Enables or disables write to TEC and REC.

0: TEC and REC can only be read

1: The same value can be written to CAN Error Counter

(TEC and REC) simultaneously (enabled only in test

mode)

FERPS

R/W

Force to Error Passive Mode

Enables to force to the error-passive state.

0: CAN Error Counter is determined by TEC/REC

1: TinyCAN behaves as the error-passive state

regardless of the TEC/REC value (enabled only in test

mode)

ATACK

R/W

Auto-Acknowledge

Enables generation of an auto-acknowledge bit in order

to execute the self-test.

0: Does not to generate its auto-acknowledge bit

1: Generates its auto-acknowledge bit (enabled only in

test mode)

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