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HD64F36022 Datasheet(PDF) 374 Page - Renesas Technology Corp |
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HD64F36022 Datasheet(HTML) 374 Page - Renesas Technology Corp |
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374 / 384 page ![]() Rev. 4.00 Sep. 23, 2005 Page 348 of 354 REJ09B0025-0400 Item Page Revision (See Manual for Details) Bit Bit Name Description 4 TCSRWE Timer Control/Status Register WD Write Enable Section 12 Watchdog Timer 12.2.1 Timer Control/Status Register WD (TCSRWD) 168 Section 14 A/D Converter 14.3.1 A/D Data Registers A to D (ADDRA to ADDRD) 220 Therefore byte access to ADDR should be done by reading the upper byte first then the lower one. Word access is also possible. ADDR is initialized to H'0000. Values Item Symbol Applicable Pins Test Condition Min V CC = 4.0 V to 5.5 V V CC × 0.7 Input high voltage V IH PB3 to PB0 V CC × 0.8 Input low voltage V IL RXD, RXD_2, RXD_3* 1, P12 to P10, P17 to P14, : PB3 to PB0 V CC = 4.0 V to 5.5 V –0.3 Section 18 Electrical Characteristics Table 18.2 DC Characteristics (1) 254 Mode RES Pin Internal State Active mode 1 Operates Active mode 2 V CC Operates ( φOSC/64) Sleep mode 1 Only timers operate Sleep mode 2 V CC Only timers operate ( φOSC/64) Table 18.2 DC Characteristics (1) 257 |
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