HD64F36022 datasheet(208/384 Pages) RENESAS

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Section 13 Serial Communication Interface 3 (SCI3)

Rev. 4.00 Sep. 23, 2005 Page 182 of 354

REJ09B0025-0400

13.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot

be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.

Bit

Bit Name

Initial

Value

R/W

Description

TDRE

R/W

Transmit Data Register Empty

Indicates whether TDR contains transmit data.

[Setting conditions]

• When the TE bit in SCR3 is 0

• When data is transferred from TDR to TSR

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the transmit data is written to TDR

RDRF

R/W

Receive Data Register Full

Indicates that the received data is stored in RDR.

[Setting condition]

• When serial reception ends normally and receive data

is transferred from RSR to RDR

[Clearing conditions]

• When 0 is written to RDRF after reading RDRF = 1

• When data is read from RDR

OER

R/W

Overrun Error

[Setting condition]

• When an overrun error occurs in reception

[Clearing condition]

• When 0 is written to OER after reading OER = 1

FER

R/W

Framing Error

[Setting condition]

• When a framing error occurs in reception

[Clearing condition]

• When 0 is written to FER after reading FER = 1

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