HD64F36022 datasheet(204/384 Pages) RENESAS

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Section 13 Serial Communication Interface 3 (SCI3)

Rev. 4.00 Sep. 23, 2005 Page 178 of 354

REJ09B0025-0400

13.3.1

Receive Shift Register (RSR)

RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into

parallel data. When one frame of data has been received, it is transferred to RDR automatically.

RSR cannot be directly accessed by the CPU.

13.3.2

Receive Data Register (RDR)

RDR is an 8-bit register that stores received data. When the SCI3 has received one frame of serial

data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is

receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive

operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only

once. RDR cannot be written to by the CPU. RDR is initialized to H'00.

13.3.3

Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first

transfers transmit data from TDR to TSR automatically, then sends the data that starts from the

LSB to the TXD pin

. TSR cannot be directly accessed by the CPU.

13.3.4

Transmit Data Register (TDR)

TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is

empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-

buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit

data has already been written to TDR during transmission of one-frame data, the SCI3 transfers

the written data to TSR to continue transmission. To achieve reliable serial transmission, write

transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is

initialized to H'FF.

HD64F36022 Datasheet(PDF) 204 Page - Renesas Technology Corp