HD64F36022 datasheet(311/384 Pages) RENESAS

311 / 384 page

Appendix

Rev. 4.00 Sep. 23, 2005 Page 285 of 354

REJ09B0025-0400

Appendix A Instruction Set

A.1

Instruction List

Operand Notation

Symbol

Description

General (destination*) register

General (source*) register

General register*

ERd

General destination register (address register or 32-bit register)

ERs

General source register (address register or 32-bit register)

ERn

General register (32-bit register)

(EAd)

Destination operand

(EAs)

Source operand

Program counter

Stack pointer

CCR

Condition-code register

N (negative) flag in CCR

Z (zero) flag in CCR

V (overflow) flag in CCR

C (carry) flag in CCR

disp

Displacement

→

Transfer from the operand on the left to the operand on the right, or transition from

the state on the left to the state on the right

Addition of the operands on both sides

–

Subtraction of the operand on the right from the operand on the left

Multiplication of the operands on both sides

Division of the operand on the left by the operand on the right

∧

Logical AND of the operands on both sides

∨

Logical OR of the operands on both sides

⊕

Logical exclusive OR of the operands on both sides

NOT (logical complement)

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