Electronic Components Datasheet Search
  English  ▼

X  

SH7670 Datasheet(PDF) 99 Page - Renesas Technology Corp

Part # SH7670
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series
PDF  1292 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7670 Datasheet(HTML) 99 Page - Renesas Technology Corp

Back Button SH7670 Datasheet HTML 95Page - Renesas Technology Corp SH7670 Datasheet HTML 96Page - Renesas Technology Corp SH7670 Datasheet HTML 97Page - Renesas Technology Corp SH7670 Datasheet HTML 98Page - Renesas Technology Corp SH7670 Datasheet HTML 99Page - Renesas Technology Corp SH7670 Datasheet HTML 100Page - Renesas Technology Corp SH7670 Datasheet HTML 101Page - Renesas Technology Corp SH7670 Datasheet HTML 102Page - Renesas Technology Corp SH7670 Datasheet HTML 103Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 99 / 1292 page
background image
Section 2 CPU
Rev. 1.00 Nov. 14, 2007 Page 73 of 1262
REJ09B0437-0100
(1)
Reset State
In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset.
(2)
Exception Handling State
The exception handling state is a transient state that occurs when exception handling sources such
as resets or interrupts alter the CPU’s processing state flow.
For a reset, the initial values of the program counter (PC) (execution start address) and stack
pointer (SP) are fetched from the exception handling vector table and stored; the CPU then
branches to the execution start address and execution of the program begins.
For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status
register (SR) are saved to the stack area. The exception service routine start address is fetched
from the exception handling vector table; the CPU then branches to that address and the program
starts executing, thereby entering the program execution state.
(3)
Program Execution State
In the program execution state, the CPU sequentially executes the program.
(4)
Power-Down State
In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP
instruction places the CPU in sleep mode or software standby mode.
(5)
Bus-Released State
In the bus-released state, the CPU releases bus to a device that has requested it.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com