SH7670 datasheet(19/1292 Pages) RENESAS

19 / 1292 page

Rev. 1.00 Nov. 14, 2007 Page xix of xxvi

Section 16 Serial Sound Interface (SSI) ............................................................585

16.1

Features............................................................................................................................. 585

16.2

Input/Output Pins .............................................................................................................. 587

16.3

Register Description ......................................................................................................... 588

16.3.1

Control Register (SSICR) ................................................................................. 589

16.3.2

Status Register (SSISR) .................................................................................... 595

16.3.3

Transmit Data Register (SSITDR) .................................................................... 600

16.3.4

Receive Data Register (SSIRDR) ..................................................................... 600

16.3.5

SSI Clock Selection Register (SCSR)............................................................... 601

16.4

Operation Description....................................................................................................... 602

16.4.1

Bus Format........................................................................................................ 602

16.4.2

Non-Compressed Modes................................................................................... 603

16.4.3

Operation Modes............................................................................................... 613

16.4.4

Transmit Operation ........................................................................................... 614

16.4.5

Receive Operation............................................................................................. 617

16.4.6

Temporary Stop and Restart Procedures in Transmit Mode ............................. 620

16.4.7

Serial Bit Clock Control.................................................................................... 621

16.5

Usage Notes ...................................................................................................................... 622

16.5.1

Limitations from Overflow during Receive DMA Operation........................... 622

Section 17 USB 2.0 Host/Function Module (USB) ...........................................623

17.1

Features............................................................................................................................. 623

17.2

Input / Output Pins............................................................................................................ 626

17.3

Register Description ......................................................................................................... 628

17.3.1

System Configuration Control Register (SYSCFG) ......................................... 635

17.3.2

CPU Bus Wait Setting Register (BUSWAIT) .................................................. 639

17.3.3

System Configuration Status Register (SYSSTS)............................................. 640

17.3.4

Device State Control Register (DVSTCTR) ..................................................... 642

17.3.5

Test Mode Register (TESTMODE) .................................................................. 648

17.3.6

DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG) ................ 651

17.3.7

FIFO Port Registers (CFIFO, D0FIFO, D1FIFO)............................................. 652

17.3.8

FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)............. 654

17.3.9

FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) ........ 661

17.3.10

Interrupts Enable Register 0 (INTENB0) ......................................................... 665

17.3.11

Interrupt Enable Register 1 (INTENB1) ........................................................... 667

17.3.12

BRDY Interrupt Enable Register (BRDYENB) ............................................... 669

17.3.13

NRDY Interrupt Enable Register (NRDYENB) ............................................... 671

17.3.14

BEMP Interrupt Enable Register (BEMPENB) ................................................ 673

17.3.15

SOF Control Register (SOFCFG) ..................................................................... 675

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