SH7670 datasheet(15/1292 Pages) RENESAS

15 / 1292 page

Rev. 1.00 Nov. 14, 2007 Page xv of xxvi

11.3.2

Software Standby Mode.................................................................................... 390

11.3.3

Software Standby Mode Application Example................................................. 392

11.3.4

Module Standby Function................................................................................. 393

11.4

Usage Notes ...................................................................................................................... 394

Section 12

Ethernet Controller (EtherC)...........................................................395

12.1

Features............................................................................................................................. 395

12.2

Input/Output Pins .............................................................................................................. 397

12.3

Register Description ......................................................................................................... 399

12.3.1

EtherC Mode Register (ECMR)........................................................................ 400

12.3.2

EtherC Status Register (ECSR)......................................................................... 403

12.3.3

EtherC Interrupt Permission Register (ECSIPR) .............................................. 405

12.3.4

PHY Interface Register (PIR) ........................................................................... 406

12.3.5

MAC Address High Register (MAHR)............................................................. 407

12.3.6

MAC Address Low Register (MALR).............................................................. 408

12.3.7

Receive Frame Length Register (RFLR) .......................................................... 409

12.3.8

PHY Status Register (PSR)............................................................................... 410

12.3.9

Transmit Retry Over Counter Register (TROCR) ............................................ 411

12.3.10

Delayed Collision Detect Counter Register (CDCR)........................................ 412

12.3.11

Lost Carrier Counter Register (LCCR) ............................................................. 413

12.3.12

Carrier Not Detect Counter Register (CNDCR) ............................................... 414

12.3.13

CRC Error Frame Counter Register (CEFCR).................................................. 415

12.3.14

Frame Receive Error Counter Register (FRECR)............................................. 416

12.3.15

Too-Short Frame Receive Counter Register (TSFRCR)................................... 417

12.3.16

Too-Long Frame Receive Counter Register (TLFRCR)................................... 418

12.3.17

Residual-Bit Frame Counter Register (RFCR) ................................................. 419

12.3.18

Multicast Address Frame Counter Register (MAFCR)..................................... 420

12.3.19

IPG Register (IPGR) ......................................................................................... 421

12.3.20

Automatic PAUSE Frame Set Register (APR) ................................................. 422

12.3.21

Manual PAUSE Frame Set Register (MPR) ..................................................... 423

12.3.22

PAUSE Frame Retransfer Count Set Register (TPAUSER)............................. 424

12.4

Operation .......................................................................................................................... 425

12.4.1

Transmission..................................................................................................... 425

12.4.2

Reception .......................................................................................................... 427

12.4.3

MII Frame Timing ............................................................................................ 428

12.4.4

Accessing MII Registers ................................................................................... 430

12.4.5

Magic Packet Detection .................................................................................... 433

12.4.6

Operation by IPG Setting.................................................................................. 434

12.4.7

Flow Control ..................................................................................................... 434

12.5

Connection to PHY-LSI.................................................................................................... 435

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