SH7670 datasheet(11/1292 Pages) RENESAS

11 / 1292 page

Rev. 1.00 Nov. 14, 2007 Page xi of xxvi

5.2.1

Input/Output Pins .............................................................................................. 113

5.2.2

Types of Reset .................................................................................................. 113

5.2.3

Power-On Reset ................................................................................................ 114

5.2.4

Manual Reset .................................................................................................... 116

5.3

Address Errors ..................................................................................................................117

5.3.1

Address Error Sources ...................................................................................... 117

5.3.2

Address Error Exception Handling ................................................................... 118

5.4

Register Bank Errors......................................................................................................... 119

5.4.1

5.4.2

5.5

Interrupts........................................................................................................................... 120

5.5.1

Interrupt Sources............................................................................................... 120

5.5.2

Interrupt Priority Level ..................................................................................... 121

5.5.3

Interrupt Exception Handling ........................................................................... 122

5.6

Exceptions Triggered by Instructions ............................................................................... 123

5.6.1

Types of Exceptions Triggered by Instructions ................................................ 123

5.6.2

Trap Instructions ............................................................................................... 124

5.6.3

Slot Illegal Instructions ..................................................................................... 124

5.6.4

General Illegal Instructions............................................................................... 124

5.6.5

Integer Division Instructions............................................................................. 125

5.6.6

Floating-Point Operation Instruction ................................................................ 126

5.7

When Exception Sources Are Not Accepted .................................................................... 127

5.8

Stack Status after Exception Handling Ends..................................................................... 128

5.9

Usage Notes ...................................................................................................................... 130

5.9.1

Value of Stack Pointer (SP) .............................................................................. 130

5.9.2

Value of Vector Base Register (VBR) .............................................................. 130

5.9.3

Address Errors Caused by Stacking of Address Error Exception Handling ..... 130

Section 6 Interrupt Controller (INTC) ...............................................................131

6.1

Features............................................................................................................................. 131

6.2

Input/Output Pins .............................................................................................................. 133

6.3

Register Descriptions ........................................................................................................ 134

6.3.1

Interrupt Priority Registers 01, 02, 06 to 16

(IPR01, IPR02, IPR06 to IPR16) ...................................................................... 135

6.3.2

Interrupt Control Register 0 (ICR0).................................................................. 137

6.3.3

Interrupt Control Register 1 (ICR1).................................................................. 138

6.3.4

IRQ Interrupt Request Register (IRQRR)......................................................... 139

6.3.5

Bank Control Register (IBCR).......................................................................... 141

6.3.6

Bank Number Register (IBNR)......................................................................... 142

6.4

Interrupt Sources...............................................................................................................143

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