SH7670 datasheet(29/1292 Pages) RENESAS

Part #	SH7670

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

PDF	1292 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

29 / 1292 page

Section 1 Overview

Rev. 1.00 Nov. 14, 2007 Page 3 of 1262

REJ09B0437-0100

Classification

Module/Function Description

CPU

• Renesas Technology original SuperH architecture

• Compatible with SH-1, SH-2, and SH-2E at object code

level

• 32-bit internal data bus

• General-register architecture

• Sixteen 32-bit general registers

• Four 32-bit control registers

• Four 32-bit system registers

• Register bank for high-speed response to interrupts

• RISC-type instruction set

(upward compatible with SH series)

• Instruction length: 16-bit fixed-length basic instructions for

improved code efficiency and 32-bit instructions for high

performance and usability

• Load/store architecture

• Delayed branch instructions

• Instruction set based on C language

• Superscalar architecture to execute two instructions at

one time including FPU

• Instruction execution time: Up to two instructions/cycle

• Address space: 4 Gbytes

• Internal multiplier

• Five-stage pipeline

• Harvard architecture

SH7670 Datasheet(PDF) 29 Page - Renesas Technology Corp