SH7750 datasheet(41/1162 Pages) RENESAS

41 / 1162 page

Rev.7.00 Oct. 10, 2008 Page xli of lxxxiv

REJ09B0366-0700

Item

Page

Revision (See Manual for Details)

22.3.4 Peripheral

Module Signal Timing

Table 22.34 Peripheral

Module Signal Timing

(3)

1007

Table and notes amended

HD6417750S

VF133 (V)

HD6417750S

VBT133 (V)

HD6417750

SF167 (V)

HD6417750

SF200 (V)

Module

Item

Symbol

Min

Max

Min

Max

Notes: 1. Pcyc: P clock cycles

2. V

DDQ = 3.0 to 3.6 V, VDD =

1.5 V, T

a = –20 to +75°C,

L = 30 pF, PLL2 on

3. V

DDQ = 3.0 to 3.6 V, VDD =

1.8 V, T

a = –20 to +75°C,

L = 30 pF, PLL2 on

4. V

DDQ = 3.0 to 3.6 V, VDD =

1.8 V, T

a = –20 to +75°C,

L = 30 pF, PLL2 on

Table 22.34 Peripheral

Module Signal Timing

(4)

1008,

1009

Table and notes amended

HD6417750

VF128 (V)

HD6417750

F167 (V)

Module

Item

Symbol

Min

Max

Min

Max

Notes: 1. Pcyc: P clock cycles

2. V

DDQ = 3.0 to 3.6 V, VDD =

1.5 V, T

a = –20 to +75°C,

L = 30 pF, PLL2 on

3. V

DDQ = 3.0 to 3.6 V, VDD =

1.8 V, T

a = –20 to +75°C,

L = 30 pF, PLL2 on

4. V

DDQ = 3.0 to 3.6 V, VDD =

1.8 V, T

a = –20 to +75°C,

L = 30 pF, PLL2 on

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