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SH7750 Datasheet(PDF) 30 Page - Renesas Technology Corp |
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SH7750 Datasheet(HTML) 30 Page - Renesas Technology Corp |
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30 / 1162 page  Rev.7.00 Oct. 10, 2008 Page xxx of lxxxiv REJ09B0366-0700 Item Page Revision (See Manual for Details) 20.2.1 Access to UBC Control Registers 854 Description amended 2. Execute instructions requiring 5 states for execution after the memory store instruction that updated the register. As the CPU executes two instructions in parallel and a minimum of 0.5 state is required for execution of one instruction, 11 instructions must be inserted. The updated value will be valid from the 6th state onward. 21.1.1 Features 879 Description amended The high-performance user debug interface (H-UDI) is a serial input/output interface supporting a subset of the JTAG, IEEE 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. 21.1.3 Pin Configuration Table 21.1 H-UDI Pins 881, 882 Note amended 3. Fixed to the ground or connected to the same signal line as RESET, or to a signal line that behaves in the same way. However, there is a problem when this pin is fixed to the ground. TRST is pulled up in the chip so, when this pin is fixed to the ground via external connection, a minute current will flow. The size of this current is determined by the rating of the pull-up resistor . Although this current has no effect on the chip's operation, unnecessary current will be dissipated. |
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