SH7750 datasheet(42/1162 Pages) RENESAS

42 / 1162 page

Rev.7.00 Oct. 10, 2008 Page xlii of lxxxiv

REJ09B0366-0700

Item

Page

Revision (See Manual for Details)

22.3.4 Peripheral

Module Signal Timing

Table 22.34 Peripheral

Module Signal Timing

(5)

1010

Table and notes amended

HD6417750

VF128 (V)

HD6417750

F167 (V)

Module

Item

Symbol

Min

Max

Min

Max

Notes: 1. Pcyc: P clock cycles

2. V

DDQ = 3.0 to 3.6 V, VDD =

1.5 V, T

a = –20 to +75°C,

L = 30 pF, PLL2 on

3. V

DDQ = 3.0 to 3.6 V, VDD =

1.8 V, T

a = –20 to +75°C,

L = 30 pF, PLL2 on

4. V

DDQ = 3.0 to 3.6 V, VDD =

1.8 V, T

a = –20 to +75°C,

L = 30 pF, PLL2 on

Appendix A Address

List

Table A.1 Address List

1017 to

1022

Table amended

Synchronization Clock

lclk

→ lck

Bclk

→ Bck

Pclk

→ Pck

Appendix B Package

Dimensions

Figure B.2 Package

Dimensions (256-Pin

BGA)

⎯

Package Dimensions deleted (Combined with figure B.1)

Figure B.4 Package

Dimensions (292-Pin

BGA)

1026

Newly added

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