SH7750 datasheet(10/1162 Pages) RENESAS

10 / 1162 page

Rev.7.00 Oct. 10, 2008 Page x of lxxxiv

REJ09B0366-0700

Item

Page

Revision (See Manual for Details)

1.4.2 Pin Functions

(208-Pin QFP)

Table 1.3 Pin

Functions

26, 27,

Table and notes amended

Memory Interface

No.

Pin Name

I/O

Function

Reset

SRAM

DRAM

SDRAM PCMCIA MPX

CKIO

Clock output

CKIO

RD/

WR RD/WR RD/WR RD/WR RD/WR

Read/write

Notes: ... VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG

are connected inside the package.

The

RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not

provided on the QFP package.

1.4.3 Pin Functions

(264-Pin CSP)

Table 1.4 Pin

Functions

35, 38,

Table and notes amended

Memory Interface

No.

Pin Name

I/O

Function

Reset

SRAM

DRAM

SDRAM PCMCIA MPX

CKIO

Clock output

CKIO

VDDQ

Power IO VDD (3.3 V)

VSSQ

Power IO GND (0 V)

CKIO2

CKIO*

CKIO

RD/

WR RD/WR RD/WR RD/WR RD/WR

Read/write

113 T12

RD/

WR2

RD/

WR RD/WR RD/WR RD/WR RD/WR

RD/

175 E14

Notes: ... Power must be supplied to VDD-RTC and VSS-RTC

regardless of whether or not the on-chip RTC is used.

NC pins must be left completely open, and not

connected to a power supply, GND, etc.

1.4.4 Pin Functions

(292-Pin BGA)

42 to 52 Newly added

2.2.1 Privileged Mode

and Banks

Table 2.1 Initial

Table amended

Type

Registers

Initial Value*

MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0,

IMASK = 1111 (H'F), reserved bits = 0, others

undefined

Control registers

2.6 Processor States

Figure 2.6 Processor

State Transitions

Figure amended

RESET = 0,

MRESET = 1

Power-on reset state

Manual reset state

From any state when

RESET = 0 and MRESET = 1

RESET = 0 and MRESET = 0

Reset state

3.8 Usage Notes

109

Newly added

4.3.1 Configuration

• LRU (SH7750R only)

119

Description amended

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