SH7750 datasheet(11/1162 Pages) RENESAS

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Rev.7.00 Oct. 10, 2008 Page xi of lxxxiv

REJ09B0366-0700

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Page

Revision (See Manual for Details)

4.3.10 Notes on Using

Cache Enhanced Mode

(SH7750R Only)

125 to

127

Newly added

4.4.1 Configuration

• LRU (SH7750R only)

130

Description amended

• LRU (SH7750R only)

In a 2-way set-associative cache, up to 2 items of data can

be registered in the cache at each entry address. When an

entry is registered, the LRU bit indicates which of the 2 ways

it is to be registered in. The LRU bit is a single bit of each

entry, and its value is controlled by hardware.

5.3.2 Exception

Handling Vector

Addresses

151

Description amended

The reset vector address is fixed at H'A000 0000. General

exception and interrupt vector addresses are determined by

adding the offset for the specific event to the vector base

address, which is set by software in the vector base register

(VBR).

5.5.3 Exception

Requests and BL Bit

158

Description amended

When the BL bit in SR is 0, general exception and interrupts are

accepted.

When the BL bit in SR is 1 and a general exception other than a

user break is generated, the CPU's internal registers and the

registers of the other modules are set to their states following a

manual reset, and the CPU branches to the same address as in

a reset (H'A000 0000).

5.6.1 Resets

(1) Power-On Reset

159

Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

(2) Manual Reset

160

Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

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