SH7750 datasheet(85/1162 Pages) RENESAS

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Section 1 Overview

Rev.7.00 Oct. 10, 2008 Page 1 of 1074

REJ09B0366-0700

Section 1 Overview

1.1

SH7750, SH7750S, SH7750R Groups Features

This LSI (SH7750, SH7750S, and SH7750R Groups) is a 32-bit RISC (reduced instruction set

computer) microprocessor with a SH-4 CPU core and features upward compatibility with SH-1,

SH-2, and SH-3 microcomputers at the instruction set level. It includes an instruction cache, an

operand cache with a choice of copy-back or write-through mode, and an MMU (memory

management unit) with a 64-entry fully-associative unified TLB (translation lookaside buffer).

The SH7750 and SH7750S have an 8-Kbyte instruction cache and a 16-Kbyte data cache. The

SH7750R has a 16-Kbyte instruction cache and a 32-Kbyte data cache.

This LSI has an on-chip bus state controller (BSC) that allows connection to DRAM and

synchronous DRAM. Its 16-bit fixed-length instruction set enables program code size to be

reduced by almost 50

% compared with 32-bit instructions.

The features of this LSI are summarized in table 1.1.

Table 1.1

LSI Features

Item

Features

LSI

• Superscalar architecture: Parallel execution of two instructions

• External buses

⎯ Separate 26-bit address and 64-bit data buses

⎯ External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus

frequency

SH7750 Datasheet(PDF) 85 Page - Renesas Technology Corp