SH7750 datasheet(12/1162 Pages) RENESAS

12 / 1162 page

Rev.7.00 Oct. 10, 2008 Page xii of lxxxiv

REJ09B0366-0700

Item

Page

Revision (See Manual for Details)

5.6.1 Resets

(3) H-UDI Reset

161

Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

(4) Instruction TLB

Multiple-Hit Exception

162

Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

(5) Operand TLB

Multiple-Hit Exception

163

Description amended

In the initialization processing, the VBR register is set to H'0000

0000, and in SR, the MD, RB, and BL bits are set to 1, the FD

bit is cleared to 0, and the interrupt mask bits (IMASK) are set

to B'1111.

...

SR.IMASK = B'1111;

5.6.2 General

Exceptions

(11) General FPU

Disable Exception

174

Note amended

Note: * FPU instructions are instructions in which the first 4 bits

of the instruction code are H'F (but excluding undefined

instruction H'FFFD), and the LDS, STS, LDS.L, and

STS.L instructions corresponding to FPUL and FPSCR.

5.6.3 Interrupts

(3) Peripheral Module

Interrupts

180

Description amended

INTEVT = H'00000400 ~ H'00000B80;

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