SH7750 datasheet(24/1162 Pages) RENESAS

24 / 1162 page

Rev.7.00 Oct. 10, 2008 Page xxiv of lxxxiv

REJ09B0366-0700

Item

Page

Revision (See Manual for Details)

14.3.2 DMA Transfer

Requests

569

Description amended

The DS bit in CHCR0/CHCR1 is used to select either falling

edge detection or low level detection for the

DREQ signal (level

detection when DS = 0, edge detection when DS = 1).

DREQ is accepted after a power-on reset if TE = 0, NMIF = 0,

and AE = 0, but transfer is not executed if DMA transfer is not

enabled (DE = 0 or DME = 0).

14.3.4 Types of DMA

Transfer

Table 14.7

Relationship between

DMA Transfer Type,

Request Mode, and Bus

Mode

582

Notes amended

Notes: 2. Auto-request, or on-chip peripheral module request

possible. If the transfer request source is the SCI

(SCIF), either the transfer source must be SCRDR1

(SCFRDR2) or the transfer destination must be

SCTDR1 (SCFTDR2).

Table 14.8 External

Request Transfer

Sources and

Destinations in Normal

DMA Mode

583

Title ameded

14.3.5 Number of Bus

Cycle States and

DREQ

Pin Sampling Timing

585

Description added

DREQ Pin Sampling Timing: In external request mode, the

DREQ pin is sampled at the rising edge of CKIO clock pulses.

When

DREQ input is detected, a DMAC bus cycle is generated

and DMA transfer executed after four CKIO cycles at the

earliest.

When falling edge detection is selected for

DREQ, the DMAC

will recognize

DREQ two cycles (CKIO) later because the

signal must pass through the asynchronous input

synchronization circuit. (There is a 1-cycle (CKIO) delay when

low-level detection is selected.)

The second and subsequent

DREQ sampling operations are

performed one cycle after the start of the first DMAC transfer

bus cycle (in the case of single address mode).

SH7750 Datasheet(PDF) 24 Page - Renesas Technology Corp

SH7750 Datasheet(HTML) 24 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL