SH7750 datasheet(29/1162 Pages) RENESAS

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Rev.7.00 Oct. 10, 2008 Page xxix of lxxxiv

REJ09B0366-0700

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19.4.1 Interrupt

Operation Sequence

843

Description and notes amended

3. The priority level of the interrupt selected by the interrupt

controller is compared with the interrupt mask bits (IMASK) in

the status register (SR) of the CPU. If the request priority

level is higher that the level in bits IMASK, the interrupt

controller accepts the interrupt and sends an interrupt

request signal to the CPU.

...

Notes: 1. The interrupt mask bits (IMASK) in the status register

(SR) are not changed by acceptance of an interrupt in

this LSI.

2. The interrupt source flag should be cleared in the

interrupt handler. To ensure that an interrupt request

that should have been cleared is not inadvertently

accepted again, read the interrupt source flag after it

has been cleared, then wait for the interval shown in

table 19.9 (Time for priority decision and SR mask bit

comparison) before clearing the BL bit or executing

an RTE instruction.

Figure 19.3 Interrupt

Operation Flowchart

844

Figure amended

Yes

Save SR to SSR;

save PC to SPC

Set interrupt source

in INTEVT

Set BL, MD, RB bits

in SR to 1

Branch to exception

handler

Level 14

interrupt?

Level 1

interrupt?

IMASK =

level 13 or

lower?

IMASK =

level 0?

Yes

Level 15

interrupt?

IMASK* =

level 14 or

lower?

Note: * IMASK: Interrupt mask bits in status register (SR)

19.6 Usage Notes

847 to

849

Newly added

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