SH7750 datasheet(23/1162 Pages) RENESAS

23 / 1162 page

Rev.7.00 Oct. 10, 2008 Page xxiii of lxxxiv

REJ09B0366-0700

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Page

Revision (See Manual for Details)

13.3.8 MPX Interface

Figure 13.68 MPX

Interface Timing 11

(Burst Write Cycle, AnW

= 0, No External Wait,

Bus Width: 32 Bits,

Transfer Data Size: 64

Bits)

523

Title amended

Figure 13.69 MPX

Interface Timing 12

(Burst Write Cycle, AnW

= 1, One External Wait

Inserted, Bus Width: 32

Bits, Transfer Data Size:

64 Bits)

524

Title amended

13.3.16 Notes on

Usage

Synchronous DRAM

Mode Register Setting

(SH7750, SH7750S

Only):

543

Notes amended

3. If synchronous DRAM mode register setting is performed

immediately following write access to the on-chip peripheral

modules*

2, the values written to the on-chip peripheral modules

cannot be guaranteed. Note that following power-on,

synchronous DRAM mode register settings should be

performed before accessing synchronous DRAM. After making

mode register settings, do not change them.

BSREQ Output in

Partial-Sharing Master

Mode

543, 544 Newly added

14.2.1 DMA Source

Address Registers 0–3

(SAR0–SAR3)

552

Description deleted

When transfer is performed from memory to an external device

with DACK in DDT mode, DTR format [31:0] is set in SAR0

[31:0]. For details, see Data Transfer Request Format in section

14.5.2, Pin in DDT Mode.

14.2.4 DMA Channel

Control Registers 0

−3

(CHCR0

−CHCR3)

Bits 13 and 12

⎯Source

Address Mode 1 and 0

(SM1, SM0):

560

Description amended

These bits specify incrementing/decrementing of the DMA

transfer source address. The specification of these bits is

ignored when data is transferred from an external device to

external memory in single address mode. For channel 0, in

DDT mode these bits are set to SM1 = 0 and SM0 = 1 with the

DTR format.

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