SH7750 datasheet(52/1162 Pages) RENESAS

52 / 1162 page

Rev.7.00 Oct. 10, 2008 Page lii of lxxxiv

REJ09B0366-0700

9.8.5

Hardware Standby Mode Timing (SH7750S, SH7750R Only) ........................... 283

9.9

Usage Notes ...................................................................................................................... 286

9.9.1

Note on Current Consumption ............................................................................. 286

Section 10 Clock Oscillation Circuits ........................................................................... 287

10.1

Overview........................................................................................................................... 287

10.1.1 Features................................................................................................................ 287

10.2

Overview of CPG.............................................................................................................. 289

10.2.1 Block Diagram of CPG........................................................................................ 289

10.2.2 CPG Pin Configuration ........................................................................................ 292

10.2.3 CPG Register Configuration ................................................................................ 292

10.3

Clock Operating Modes .................................................................................................... 293

10.4

CPG Register Description................................................................................................. 295

10.4.1 Frequency Control Register (FRQCR)................................................................. 295

10.5

Changing the Frequency ................................................................................................... 298

10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off) ........... 298

10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On) ............ 298

10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On) ...................... 299

10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off) ..................... 299

10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ............................... 299

10.6

Output Clock Control........................................................................................................ 299

10.7

Overview of Watchdog Timer .......................................................................................... 300

10.7.1 Block Diagram..................................................................................................... 300

10.7.2 Register Configuration......................................................................................... 301

10.8

WDT Register Descriptions .............................................................................................. 301

10.8.1 Watchdog Timer Counter (WTCNT)................................................................... 301

10.8.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 302

10.8.3 Notes on Register Access..................................................................................... 305

10.9

Using the WDT ................................................................................................................. 305

10.9.1 Standby Clearing Procedure ................................................................................ 305

10.9.2 Frequency Changing Procedure ........................................................................... 306

10.9.3 Using Watchdog Timer Mode.............................................................................. 306

10.9.4 Using Interval Timer Mode ................................................................................. 307

10.10 Notes on Board Design ..................................................................................................... 307

10.11 Usage Notes ...................................................................................................................... 309

10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S) .. 309

Section 11 Realtime Clock (RTC).................................................................................. 311

11.1

Overview........................................................................................................................... 311

11.1.1 Features................................................................................................................ 311

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