SH7750 datasheet(18/1162 Pages) RENESAS

18 / 1162 page

Rev.7.00 Oct. 10, 2008 Page xviii of lxxxiv

REJ09B0366-0700

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Page

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13.2.8 Memory Control

Bit 31—RAS Down

(RASD):

402

Description and table amended

Do not set RAS down mode in slave mode or partial-sharing

mode, or when areas 2 and 3 are both designated as

synchronous DRAM interface. See Connecting a 128-Mbit/256-

Mbit Synchronous DRAM with 64-bit Bus Width (SH7750R

Only): in section 13.3.5, Synchronous DRAM Interface.

Bit 31: RASD

Description

(Initial value)

Auto-precharge mode

Bits 29 to 27—RAS

Precharge Time at End

of Refresh (TRC2–

TRC0)

402

Note added

Note: For setting values and the period during which no

command is issued, see 22.3.3, Bus Timing.

Bits 21 to 19—RAS

Precharge Period

(TPC2–TPC0):

403

Description amended and note added

When the DRAM interface is selected, these bits specify the

minimum number of cycles until

RAS is asserted again after

being negated. When the synchronous DRAM interface is

selected, these bits specify the minimum number of cycles until

the next bank active command

after precharging.

Note: For setting values and the period during which no

command is issued, see 22.3.3, Bus Timing.

Bits 15 to 13—Write

Precharge Delay

(TRWL2–TRWL0):

404

Description amended and note added

After a write cycle, the next active command is not issued for a

period equivalent to the

setting values of the TPC[2:0] and

TRWL[2:0] bits.* ...

Note: * For setting values and the period during which no

command is issued, see 22.3.3, Bus Timing.

Bits 12 to 10—CAS-

Before-RAS Refresh

RAS Assertion Period

(TRAS2–TRAS0):

405

Description amended and note added

When the DRAM interface is set, these bits set the

RAS

assertion period in CAS-before-RAS refreshing. When the

synchronous DRAM interface is set, the bank active command

is not issued for the period set by the TRC[2:0]* and TRAS[2:0]

bits after an auto-refresh command is issued.

Note: For setting values and the period during which no

command is issued, see 22.3.3, Bus Timing.

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