SH7750 datasheet(19/1162 Pages) RENESAS

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Rev.7.00 Oct. 10, 2008 Page xix of lxxxiv

REJ09B0366-0700

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13.3.4 DRAM Interface

Refresh Timing:

• Self-Refresh

463

Description deleted

After the self-refresh is cleared, the refresh controller

immediately generates a refresh request. The RAS precharge

time immediately after the end of the self-refreshing can be set

by bits TRC2–TRC0 in MCR.

CAS-before-RAS refreshing is performed in normal operation,

in sleep mode, and in the case of a manual reset.

13.3.5 Synchronous

DRAM Interface

465

Description amended

With this LSI, burst read/burst write mode is supported as the

synchronous DRAM operating mode. The data bus width is 32

or 64 bits, and the SZ size bits in MCR must be set to 00 or 11.

The burst enable bit (BE) in MCR is ignored, a 32-byte burst

transfer is performed in a cache fill/copy-back cycle, and in a

write-through area write or a non-cacheable area read/write,

32-byte data is read even in a single read in order to access

synchronous DRAM with a burst read/write access. 32-byte

data transfer is also performed in a single write, but DQMn is

not asserted when unnecessary data is transferred. For details

on the burst length, see section 13.2.10, Synchronous DRAM

Mode Register (SDMR), and Power-On Sequence in section

13.3.5, Synchronous DRAM Interface. The SH7750R Group

supports burst read and burst write operations with a burst

length of 4 as a synchronous DRAM operating mode when

using a 32-bit data bus. The burst enable (BE) bit in MCR is

ignored, and a 32-byte burst transfer is performed in a cache fill

or copy-back cycle. In write-through area write operations and

non-cacheable area read or write operations, 16 bytes of data

is read even in a single read because burst read or write

accesses to synchronous DRAM use a burst length of 4.

Sixteen bytes of data is transferred in the case of a single write

also, but DQMn is not asserted when unnecessary data is

transferred.

For changing the burst length (a function only available in the

SH7750R) for a 32-bit bus, see Notes on Changing the Burst

Length (SH7750R Only) in section 13.3.5, Synchronous DRAM

Interface.

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