SH7750 datasheet(55/1162 Pages) RENESAS

55 / 1162 page

Rev.7.00 Oct. 10, 2008 Page lv of lxxxiv

REJ09B0366-0700

13.2.14 Refresh Count Register (RFCR) .......................................................................... 420

13.2.15 Notes on Accessing Refresh Control Registers.................................................... 420

13.3

Operation........................................................................................................................... 421

13.3.1 Endian/Access Size and Data Alignment............................................................. 421

13.3.2 Areas .................................................................................................................... 433

13.3.3 SRAM Interface ................................................................................................... 438

13.3.4 DRAM Interface .................................................................................................. 447

13.3.5 Synchronous DRAM Interface............................................................................. 465

13.3.6 Burst ROM Interface............................................................................................ 497

13.3.7 PCMCIA Interface ............................................................................................... 500

13.3.8 MPX Interface...................................................................................................... 511

13.3.9 Byte Control SRAM Interface ............................................................................. 529

13.3.10 Waits between Access Cycles.............................................................................. 534

13.3.11 Bus Arbitration..................................................................................................... 536

13.3.12 Master Mode ........................................................................................................ 539

13.3.13 Slave Mode .......................................................................................................... 540

13.3.14 Partial-Sharing Master Mode ............................................................................... 541

13.3.15 Cooperation between Master and Slave ............................................................... 542

13.3.16 Notes on Usage .................................................................................................... 543

Section 14 Direct Memory Access Controller (DMAC).......................................... 545

14.1

Overview........................................................................................................................... 545

14.1.1 Features................................................................................................................ 545

14.1.2 Block Diagram (SH7750, SH7750S) ................................................................... 547

14.1.3 Pin Configuration (SH7750, SH7750S) ............................................................... 549

14.1.4 Register Configuration (SH7750, SH7750S) ....................................................... 550

14.2

14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 552

14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 553

14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 554

14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 555

14.2.5 DMA Operation Register (DMAOR)................................................................... 564

14.3

Operation........................................................................................................................... 567

14.3.1 DMA Transfer Procedure..................................................................................... 567

14.3.2 DMA Transfer Requests ...................................................................................... 569

14.3.3 Channel Priorities................................................................................................. 573

14.3.4 Types of DMA Transfer....................................................................................... 576

14.3.5 Number of Bus Cycle States and

DREQ Pin Sampling Timing .......................... 585

14.3.6 Ending DMA Transfer ......................................................................................... 599

14.4

Examples of Use ............................................................................................................... 602

SH7750 Datasheet(PDF) 55 Page - Renesas Technology Corp

SH7750 Datasheet(HTML) 55 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL