SH7750 datasheet(80/1162 Pages) RENESAS

80 / 1162 page

Rev.7.00 Oct. 10, 2008 Page lxxx of lxxxiv

REJ09B0366-0700

Table 14.16 Function of

BAVL ................................................................................................. 648

Table 14.17 DTR Format for Clearing Request Queues ............................................................ 649

Table 14.18 DMAC Interrupt-Request Codes............................................................................ 650

Section 15 Serial Communication Interface (SCI)

Table 15.1

SCI Pins.................................................................................................................. 658

Table 15.2

SCI Registers.......................................................................................................... 659

Table 15.3

Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ................. 677

Table 15.4

Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode.................... 681

Table 15.5

Maximum Bit Rate for Various Frequencies with Baud Rate Generator

(Asynchronous Mode)............................................................................................ 682

Table 15.6

Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 683

Table 15.7

Maximum Bit Rate with External Clock Input (Synchronous Mode) .................... 683

Table 15.8

SCSMR1 Settings for Serial Transfer Format Selection ........................................ 685

Table 15.9

SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection.......................... 686

Table 15.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 688

Table 15.11 Receive Error Conditions ....................................................................................... 696

Table 15.12 SCI Interrupt Sources ............................................................................................. 718

Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data.............................................. 719

Table 15.14 Peripheral Module Signal Timing .......................................................................... 724

Section 16 Serial Communication Interface with FIFO (SCIF)

Table 16.1

SCIF Pins ............................................................................................................... 728

Table 16.2

SCIF Registers ....................................................................................................... 729

Table 16.3

SCSMR2 Settings for Serial Transfer Format Selection ........................................ 758

Table 16.4

SCSCR2 Settings for SCIF Clock Source Selection .............................................. 758

Table 16.5

Serial Transmit/Receive Formats ........................................................................... 759

Table 16.6

SCIF Interrupt Sources........................................................................................... 770

Section 17 Smart Card Interface

Table 17.1

Smart Card Interface Pins ...................................................................................... 777

Table 17.2

Smart Card Interface Registers............................................................................... 777

Table 17.3

Smart Card Interface Register Settings .................................................................. 785

Table 17.4

Values of n and Corresponding CKS1 and CKS0 Settings .................................... 788

Table 17.5

Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) ....... 788

Table 17.6

Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) .................... 788

Table 17.7

Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ............ 789

Table 17.8

Table 17.9

Smart Card Mode Operating States and Interrupt Sources..................................... 796

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