32186 datasheet(413/1032 Pages) RENESAS

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10.4 TIO (Input/Output-Related 16-Bit Timer)

MULTIJUNCTION TIMERS

10-117

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function)

(1) Outline of TIO single-shot output mode

In single-shot output mode, the timer generates a pulse in width of "reload 0 register set value + 1" only once

and then stops.

When the timer is enabled " by writing to the enable bit in software or by external input "after setting the

reload 0 register, the counter is loaded with the content of the "reload 0 register -1" and starts counting

synchronously with the count clock at the next cycle. The counter counts down and when the minimum

count is reached, stops upon underflow.

The F/F output waveform in single-shot output mode is inverted " F/F output level changes from "L" to "H" or

vice versa" at startup and upon underflow, generating a single-shot pulse waveform in width of " reload 0

Furthermore, it is possible to generate an interrupt request and a DMA transfer request (for only the TIO8

and TIO9) upon underflow of the counter.

The count value is " reload 0 register set value + 1." (For counting operation, see also Section 10.3.9,

“Operation of TOP Single-shot Output Mode.” )

(2) Precautions about using TIO single-shot output mode

The following describes precautions to be observed when using TIO single-shot output mode.

• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,

the former has priority so that the counter stops.

• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the

enable bit, the latter has priority so that count is enabled.

• If the timer is enabled by external input in the same clock period as count is disabled by writing to the

enable bit, the latter has priority so that count is disabled.

• Because the timer operates synchronously with the count clock, up to one count clock-dependent delay

is generated before F/F output is inverted after writing to the enable bit.

32186 Datasheet(PDF) 413 Page - Renesas Technology Corp