32186 datasheet(598/1032 Pages) RENESAS

598 / 1032 page

SERIAL INTERFACE

12-50

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.6.4 Starting UART Transmission

The serial interface starts a transmit operation when all of the following conditions are met after being

initialized.

• SIO Transmit Control Register TEN (Transmit Enable) bit is set to "1" (Note 1).

• Transmit data is written to the SIO Transmit Buffer Register (transmit buffer empty bit = "0").

Note 1: While the transmit enable bit is cleared to "0," writes to the transmit buffer are ignored. Always be

sure to set the transmit enable bit to "1" before writing to the transmit buffer register.

When transmission starts, the serial interface sends data following the procedure described below.

• Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register.

• Set the transmit buffer empty bit to "1" (Note 2).

• Start sending data synchronously with the shift clock.

Note 2: A transmit interrupt request can be generated for reasons that the transmit buffer is empty or

transmission has finished. Also, a DMA transfer request can be generated when the transmit buffer

is empty. No DMA transfer requests can be generated for reasons that transmission has finished.

12.6.5 Successive UART Transmission

Once data has been transferred from the transmit buffer register to the transmit shift register, the next data

can be written to the transmit buffer register even when the serial interface has not finished sending the

previous data. If the next data is written to the transmit buffer before transmission has finished, the previ-

ous and the next data are transmitted successively.

Check the SIO Transmit Control Register’s transmit buffer empty flag to see if data has been transferred

from the transmit buffer register to the transmit shift register.

12.6.6 Processing at End of UART Transmission

When data transmission finishes, the following operation is automatically performed in hardware.

(1) When not transmitting successively

• The transmit status bit is cleared to "0."

(2) When transmitting successively

• When transmission of the last data in a consecutive data train finishes, the transmit status bit is

cleared to "0."

12.6.7 Transmit Interrupts

(1) Transmit buffer empty interrupt

If the transmit buffer empty interrupt was selected using the SIO Interrupt Request Source Select

the transmit buffer register to the transmit shift register. A transmit buffer empty interrupt request is

also generated when the TEN (Transmit Enable) bit is set to "1" (reenabled after being disabled) while

the transmit buffer empty interrupt has been enabled.

12.6 Transmit Operation in UART Mode

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