32186 datasheet(600/1032 Pages) RENESAS

600 / 1032 page

SERIAL INTERFACE

12-52

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.6.9 Example of UART Transmit Operation

The following shows a typical transmit operation in UART mode.

TXD

RXD

Transmit enable bit

Transmit buffer

empty bit

PAR

Write to the

transmit buffer

Transmit status bit

TXD

SIO transmit interrupt request (Note 1)

Set

Cleared

: Processing by software

: Interrupt request generated

Cleared

Transferred from the transmit buffer

to the transmit shift register

(transmission starts)

Set

Interrupt request accepted (Note 4)

(Note 2)(Note 6)

(Note 3)(Note 7)

(Note 2)

(Note 5)

Transmit

interrupt request

Transmit interrupt request

Interrupt request accepted (Note 4)

(When transmit buffer empty

interrupt is selected)

(When transmission finished

interrupt is selected)

Note 1: Changes of the Interrupt Controller's SIO Transmit Interrupt Control Register interrupt request bit

Note 2: When transmit buffer empty interrupt is enabled (DMA transfer can also be requested at the same time)

Note 3: When transmission finished interrupt is enable

Note 4: The Interrupt Controller's IVECT register is read or the SIO Transmit Interrupt Control Register interrupt request bit cleared

Note 5: A transmit interrupt request is generated when transmission is enabled.

Note 6: Be aware that even after transmit data is written to the transmit buffer, a transmit interrupt request is generated when the

data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied.

Note 7: A transmission finished interrupt request is generated when data in the transmit shift register has all been transmitted.

Figure 12.6.5 Example of UART Transmission (Transmitted Only Once)

12.6 Transmit Operation in UART Mode

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