32186 datasheet(604/1032 Pages) RENESAS

604 / 1032 page

SERIAL INTERFACE

12-56

32185/32186 Group Hardware Manual

Rev.1.10 REJ09B0235-0110 May 15, 07

12.7.2 Starting UART Reception

The serial interface starts receive operation when all of the following conditions are met after being initialized.

• SIO Receive Control Register receive enable bit is set to "1"

• Start bit (falling edge signal) is applied to the RXD pin

When the above conditions are met, the serial interface enters UART receive operation. However, the start

bit is checked again at the first rise of the internal receive shift clock and if it is detected "H" for reasons of

noise, etc., the serial interface stops receive operation and waits for the start bit again.

12.7.3 Processing at End of UART Reception

When data reception finishes, the following operation is automatically performed in hardware.

(1) When reception is completed normally

The reception finished (receive buffer full) bit is set to "1."

Notes: • An interrupt request is generated if the reception finished (receive buffer full) interrupt has

been enabled.

• A DMA transfer request is generated.

(2) When a receive error occurred

If an error occurred, the corresponding error bit (OE, FE or PE) and the receive error sum bit are set to "1,"

Notes: • If the reception finished interrupt has been selected (by SIO Receive Interrupt Request Source

Select Register), a reception finished interrupt request is generated when interrupt requests are

enabled. However, this does not apply when the detected error is an overrun error, in which

case no reception finished interrupt requests are generated.

• If the receive error interrupt has been selected (by SIO Receive Interrupt Request Source Select

• No DMA transfer requests are generated.

12.7 Receive Operation in UART Mode

32186 Datasheet(PDF) 604 Page - Renesas Technology Corp